As known, phase change memories use a class of materials that have the property of switching between two phases having distinct electrical characteristics, associated to two different crystallographic structures of the material, and precisely an amorphous, disorderly phase and a crystalline or polycrystalline, orderly phase. The two phases are hence associated to resistivities of considerably different values.
Currently, the alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can be used advantageously in phase change memory cells. The currently most promising chalcogenide is formed from an alloy of Ge, Sb and Te (Ge2Sb2Te5), which is now widely used for storing information on overwritable disks and has been also proposed for mass storage.
In the chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa.
Phase change can be obtained by locally increasing the temperature. Below 150° C., both phases are stable. Starting from an amorphous state, and rising the temperature above 200° C., there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. To bring the chalcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600° C.) and then rapidly cool off the chalcogenide.
Memory devices exploiting the properties of chalcogenic materials (also called phase change memory devices) have been already proposed.
In a phase change memory including chalcogenic elements as a storage element, memory cells are arranged in rows and columns to form an array, as shown in FIG. 1. The memory array 1 of FIG. 1 comprises a plurality of memory cells 2, each including a memory element 3 of the phase change type and a selection element 4. The memory cells 2 are interposed at cross-points between rows 6 (also called word lines) and columns 5 (also called bitlines).
In each memory cell 2, the memory element 3 has a first terminal connected to an own wordline 6 and a second terminal connected to a first terminal of an own selection element 4. The selection element 4 has a second terminal connected a bitline 5. In another solution, the memory element 3 and the selection element 4 of each cell 2 may be exchanged in position.
The composition of chalcogenides suitable for the use in a phase change memory device and a possible structure of a phase change memory cell are disclosed in a number of documents (see, e.g., U.S. Pat. No. 5,825,046).
Phase change memory cells comprise a chalcogenic material (forming a proper storage element) and a resistive electrode, also called heater (see. e.g., EP-A-1 326 254, corresponding to US-A-2003/0185047).
From an electrical point of view, the crystallization temperature and the melting temperature are obtained by causing an electric current to flow through the resistive electrode in contact or close proximity with the chalcogenic material and thus heating the chalcogenic material by Joule effect.
In particular, when the chalcogenic material is in the amorphous, high resistivity state (also called the reset state), it is necessary to apply a voltage/current pulse of a suitable length and amplitude and allow the chalcogenic material to cool slowly. In this condition, the chalcogenic material changes its state and switches from a high resistivity to a low resistivity state (also called the set state).
Vice versa, when the chalcogenic material is in the set state, it is necessary to apply a voltage/current pulse of suitable length and high amplitude so as to cause the chalcogenic material to switch to the amorphous phase.
The selection element is implemented by a switching device, such as a PN diode, a bipolar junction transistor or a MOS transistor.
For example, U.S. Pat. No. 5,912,839 describes a universal memory element using chalcogenides and including a diode as a switching element. The diode may comprise a thin film such as polycrystalline silicon or other materials.
GB-A-1 296 712 and U.S. Pat. No. 3,573,757 disclose a binary memory formed by an array of cells including a switch element called “ovonic threshold switch” (also referred to as an OTS hereinafter), connected in series with a phase change memory element PCM also called “ovonic memory switch”. The OTS and the PCM are formed adjacent to each other on an insulating substrate and are connected to each other through a conducting strip. FIG. 2a shows the electrical equivalent of a memory cell 2 having a memory element 3 and an ovonic switch 4.
The PCM is formed by a chalcogenic semiconductor material having two distinct metastable phases (crystalline and amorphous) associated to different resistivities, while the OTS is built with a chalcogenic semiconductor material having one single phase (generally amorphous, but sometimes crystalline) with two distinct regions of operation associated to different resistivities. If the OTS and the PCM have substantially different high resistances, namely with the OTS having a higher resistance than the PCM, when a memory cell is to read, a voltage drop is applied to the cell that is insufficient to trigger the PCM when the latter is in its high resistance condition (associated with a digital “0” state), but is sufficient to drive the OTS in its low resistance condition when the PCM is already in its low resistance condition (associated with a digital “1” state).
OTS (see, e.g., U.S. Pat. No. 3,271,591 and US2006073652, describing its use in connection with memory elements of the phase change type) have the characteristic shown in FIG. 2b; FIG. 2c shows the characteristic of a reset memory element PCM (with continuous line) and the characteristic of a set PCM (with dashed line).
As shown in FIG. 2b, an OTS has a high resistance for voltages below a threshold value Vth,OTS; when the applied voltage exceeds the threshold value Vth,OTS, the switch begins to conduct at a substantially constant, low voltage and has a low impedance. In this condition, if the PCM is set, as visible from FIG. 2c, the memory cell is on, if the PCM is reset, the memory cell is off.
When the current through the OTS falls below a holding current IH, the OTS goes back to his high-impedance condition. This behavior is symmetrical and occurs also for negative voltages and currents (not shown).
As shown in FIG. 2c, in the amorphous state (reset) a PCM has a plot similar to the plot of an OTS; when crystalline, the PCM has a higher conductance in the lower portion of the characteristic and about the same behaviour of the reset cell in the upper portion.
In OTS, the threshold voltage Vth is subject to a drift. The threshold voltage drift is harmful for OTS-selected memory arrays, because it could prevent the storage element of chalcogenic material from being correctly read.
In fact, as immediately recognizable from the comparative observation of FIGS. 2b and 2c, if the threshold voltage Vth of the selector is not known with satisfactory precision, and the chalcogenic storage element is crystalline (and thus stores a logical “1”) it could be read as a logical “0” because, at the reading voltage, the selector has not yet switched to the conductive state. Analogously, a reading error may occur if the chalcogenic storage element is amorphous (and thus stores a logical “0”) but at the reading voltage the element is already in the higher portion of the curve of FIG. 2c. 
In other words, the ideal reading voltage is limited between the threshold voltage of the OTS (Vth,OTS) and the sum of both threshold voltages (Vth,OTS+Vth,PCM) and the exact knowledge of Vth,OTS is thus crucial in order to maximize the reading window.
In general, it may be impossible to determine the value of a stored bit if the threshold of the selector switch is not known.
To solve this problem, peculiar chalcogenide materials are being tested that do not show drift. In the alternative, or as an additional solution, electrode materials are being studied that are able to reduce this problem. However, currently all the materials suitable for the use in phase change memory devices are affected by the threshold drift.
Furthermore, it has been noted that also PCMs undergo a drift of the reset resistance (Rreset) with time, which causes a variation in the slope of the curves in FIG. 2c. The drift in the reset resistance poses some problems for multilevel storage based on phase change memories, because intermediate levels of crystallization, corresponding to different levels of resistance, are used to store different bits. Thus, the resistance drift may cause reading errors.